Design Methodologies for Low Power VLSI Architecture

Present generation of electronic design scenario demands low power architectures. In earlier days, power was secondary as the field was premature and main concerns of design engineers were size, throughput and cost. However trade off exists between the metrics namely, size, throughput, cost and power according to the famous design metric competition theory of VLSI systems wherein improving one deteriorates the other metric. The performance of any circuit is affected greatly by its components. Optimization of the design is accomplished by compromising design issues as well as components. With the ever-shrinking technology, especially below 90 nm, power dissipation and its management has been critical for the design engineers. Significance of optimization has been understood from the fact that how important it is to have an extended battery life and at the same time reducing the package cost. This paper presents a literature review upon the strategies and methodologies in designing low power VLSI systems.